PCIe Checker Library Generation Of Sequences & Driver Component For EP LTSSM USING UVM

Paper Topic :

Network Performance; Protocols; Sensors

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Abstract :

Verification of complex systems like PCIe in SystemVerilog is a complicated process for a verification engineer, but if we adopt a standard methodology like UVM we can reduce time to verify and hence increase the efficiency. One can exploit object oriented programming to the core in UVM rather than using SystemVerilog. The objective of the project is to construct a PCIe checker library which verifies LTSSM of PCIe i.e passive monitor which can be hooked on a PCIe interface connecting different PCIe devices. The devices can be upstream or downstream. I

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