Design sram using finfet

Paper Topic :

VLSI Algorithms

Author Name :

Rashmi Verma

Abstract :

As CMOS technology shows certain limitations on the devices, also as such the device is reduced more and more in the nanometer regime out of which power dissipation, current leakages, doping, and channel length is an important issue. FinFET is evolving to be a promising technology in this regard. In this the designing, modeling and optimizing the 6-T SRAM cell device is done. Intrinsic variations and leakage control in today’s world, is very difficult to achieve, So bulk-Si MOSFETs limit the scaling of SRAM.

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