Simulation of intend model of full adder in MVL

Paper Topic :

VLSI Algorithms

Author Name :

Ankush D. Dhanorkar

Abstract :

The binary logic has become tedious and cumbersome in the advancement. Multiple value logic significantly make possible for more data to be packed within a single digit. Now present devices are implemented only in binary system, a system is necessary to evolve a system that can built the circuit in multiple value logic system. Many designers have intended their models in two value and four value logic using 0.18µm CMOS technology. Some authors concentrated on put back in place of two value logic with MVL or quaternary logic to prevail over the limitation of interconnections. Second is that for half and full adder (for addition/ arithmetic operations) the quaternary logic method required the conversion of quaternary logic level into binary level for implementation. Our aim is to intend and develop MVL or quaternary logic for full adder without converting these levels to binary logic. It will reduce the one additional step and improve the performance offer less chip size, saving more power. MVL or quaternary logic can be implemented in three different modes. From that mode, voltage mode type model is beneficial to design and give high performance with less dynamic power dissipation. The design is targeted for the 0.18 µm CMOS technology. Design tool for simulation will be ADS [ADVANCED DESIGN SYSTEM] software.

Download Article