Impact of Process Variation on 3T 1D DRAM

Paper Topic :

Expert approaches

Author Name :

Yogesh N. Thakare, Dr. Sujata N. Kale

Abstract :

Nowadays semiconductor memory is capable to store large data. Traditionally due to high speed operation, large noise margin and logic compatibility SRAM was the most popular embedded memory. However, due to its large cell area and high power consumption, SRAM has limitations when expanding the array size beyond a certain level in process variation. The process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. The design and analysis of capacitorless (with gated diode) DRAM cell to develop process variation architectures with the help of tanner tool. Day by day with continued technology scaling, process variations will be especially essential to three transistor- one diode dynamic memory structures (3T-1D DRAM).

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